The majority of connection between parts of an integrated circuit are made by low resistance metal steps which are called metal interconnects. Three levels are now being necessary. Generally, the active semiconductor portions of an integrated circuit are coated with an insulative dielectric layer and the metal interconnects are laid down in parallel strips on top of these insulator layers using photolithographic techniques. Until recently, the majority of integrated circuits employed two levels of interconnects. Each level is comprised of a plurality of separated metal strip interconnects formed on the surface of a dielectric. Each interconnect level has to be lithographically patterned, metallized, coated with dielectric and planarized.
There are many processes for forming the interlevel dielectric layers. Generally, the interconnect dielectric fill steps and the planarization step are separate steps. After the interconnect dielectric spaces are filled with oxide, the surface is uneven and needs smoothing. One common planarization technique called CVD etchback employs spin-on-glass (SOG) (or a resist) in conjunction with chemical vapor deposition (CVD) of an oxide to smooth the oxide surface. SOG is easy and fast to apply and harden. The application of SOG alone as a planarizing layer has also been reported. However SOG is not successful if used alone as a dielectric for filling interconnect spaces. Simple SOG fill is not adequate for various reasons including cracking during curing due to shrinkage when aspect ratios are low, i.e. less than 1.
One technique described in U.S. Pat. No. 5,119,164 uses SOG in interconnect fill and overcomes the cracking problems but allows the SOG to remain on the finished circuit. It is reported that SOG can cause deterioration and shift in the threshold levels of transistors if the SOG is allowed to remain permanently on the integrated circuit.
In the CVD/SOG etchback interlayer planarization process, conformal thick CVD layers are overlain with SOG, then the surface is etched back until the surface is flat. In these processes, SOG is frequently allowed to remain in place on the circuit in the very lowest regions. Usually, the surface including the SOG is then overlain with thick CVD oxide to form a smooth surface.
As depicted in FIG. 4 of the U.S. Pat. No. 5,119,164 when using SOG, narrow spaces between the SOG plug and the metal interconnect strips would not fill with SOG during spin, leaving void spaces as, i.e. so called "keyholes", indicated in that patent. In certain instances, the voids can be beneficial because they have a very high dielectric constant. However, in general, the voids are undesirable especially if there are any subsequent etch steps in the process.
With reference to FIG. 1 of this patent, it is known in interconnect space fill processes using CVD oxide that void areas called "keyholes" form in the oxide 10 in the region between the metal strips 2 and 2'. It is known that the void situation can be overcome, as depicted in FIG. 2 by sloping the sidewalls of the gap 6. This is accomplished by RIE etching, employing so called "etch back" of the oxide, the result of which is illustrated in FIG. 2A and 2B. The etchback creates oxide fillets, 5 and 5' along the side walls of metal strip interconnects 2 and 2'. In order to assure that the slope is as large as possible, the oxide is removed all the way down to the top of the metal 2. Frequently, this results in etching vertically into and beneath the underlying dielectric surface 3, forming a small trench space, 6. This trench forms because the distance between the interconnects is frequently less than the thickness of the oxide layer to be etched away. After the etchback, CVD oxide is again deposited over the metal interconnects of FIG. 2A and because of the sloped shape caused by the fillets 5 and 5', the space between the interconnects fills completely with oxide as in FIG. 2B without forming the voids such as those shown in FIG. 1. Note that the surface 10 is still not smooth and that planarization steps are required.
This voidless dielectric etchback prior art technique of FIG. 2A and 2B for forming the interlevel dielectric has only been successful to fill the spaces between level 1 interconnects without keyholes where the interconnects are less than 0.6 microns high and the spaces between them is greater than 0.5 microns wide. Level 1 is the metal closest to the active circuits. In the available etching equipment, metal layers 2 and 3 are only able to be successfully filled, i.e. without voids, for spaces up to 1.0 microns high and for widths greater than 0.8 microns wide. For spaces of width less than 0.8 microns wide, in layers 2 and/or 3, oxide keyhole voids are likely to form using the etchback fillet procedure.
As the density of devices and interconnections on integrated circuits has increased, a need has developed for a process providing voidless levels 2/3 dielectric for interconnect spacings less than 0.8 microns in width.